Accepted Papers

  • CARRY-FREE ARITHMETIC IMPLEMENTATIONS IN VERILOG
    Vikram Voleti,International Institute of Information Technology, India.
    ABSTRACT

    This paper uses Recoded Binary Signed Digits to perform carry-free arithmetic operations of addition, subtraction and multiplication on binary numbers. It compares the path delays and circuit utilizations with standard implementations, and analyzes the problem of implementing carry-free arithmetic.

  • Challenges and Mitigations of migrating a native UVM Testbench from Simulation to Emulation
    Vikas Billa, Microsemi India Pvt. Ltd., India.
    ABSTRACT

    Today°«s traditional verification flow involves verification at multiple abstraction levels; accordingly the testbench needs to be adjusted/modified from RTL simulation to hardware acceleration/emulation. Simulation offers a great springiness in debugging and the emulation offers mammoth performance gain, an ideal solution is to make use of these offerings to develop a single, unified testbench that can be used for both simulation and emulation platforms, which helps in enhancing the overall performance, productivity and faster verification closure. In this paper, we will discuss a case study based on one of our native UVM testbench, we partitioned the testbench into two top architecture that can be used not only for software simulation, but also for hardware acceleration/emulation without compromising on simulation competences such as coverage-driven, constraint-random and assertion-based verification techniques. We will also touch upon on the performance improvements, coding guidelines in developing the accelerated testbench and the efforts required for porting it from the native simulation UVM testbench. The key for the future projects is to plan the emulation ready as soon as we start the testbench development to avoid creating extra work. Creating emulation-ready testbench needs careful architectural consideration, but the performance benefits will be substantial.

  • An Anti-Radiation CPPLL in 65-nm CMOS Technology
    Qiancheng Guo and Yang Guo,Institute of microelectronics and microprocessor,China
    ABSTRACT

    Phase-locked-loop(PLL) is widely used in communication systems to generate clock signals with phase locked by external input reference signals. However, single-eventtransient( SET) effects have significant influences on the working condition of PLL, and often make it reacquire phase. This paper presents a novel radiation-hardened-by-designed CPPLL designed in a commercial 65nm CMOS process with dual-modeinterlocking (DMI) technique to eliminate SET Sensitivity of PLL. Designers need not change the structure of sub-circuits with this technique, which can simplify the design complexity. Simulation results show that the proposed RHDB CPPLL can not only mitigate SET sensitivity effectively, but also realize high circuit performance. The proposed CPPLL operates under a 1.2V power supply and consumes only 12.54mW of power at 1GHz output frequency.